Design of 16-Bit SAR ADC Using DTMOS Technique

This paper presents a 16-bit 100MS/s SAR ADC with 1V power supply for biomedical implant systems developed low technique i.e., DTMOS logic. It consists of R-2R DAC, low-power comparator, digital logic low-leakage. The designed comparator is differential architecture that has used to have an excellent, common-mode noise rejection. Comparator was created proper operation remain in saturation and could be amplifier. the chief block consumption, so we focused mainly much ability make design this module. using Cadence virtuoso CMOS 45nm technology. For SFDR, SNR, ENOB converter utilizes 63.97dB, 51.06 dB, 15.15 528.8uw.